Altera Cyclone V Device Handbook page 87

4-30
External Feedback Mode
One of the dual-purpose external clock outputs becomes the
feedback input pin,
remove clock delay and skew between devices.
When using EFB mode, you must use the same I/O standard on the input clock, feedback input, and clock
outputs.
This mode is supported only on the corner fractional PLLs. For Cyclone V E A2 and A4 devices, and
Cyclone V GX C3 device, EFB mode is supported only on the left corner fractional PLLs.
Figure 4-31: EFB Mode in Cyclone V Devices
inclk
N PFD CP/LF
÷
Figure 4-32: Example of Phase Relationship Between the PLL Clocks in EFB Mode
Altera Corporation
is phase-aligned with the clock input pin. Aligning these clocks allows you to
fbin
C0
C1
C2
C3
VCO 0
Multiplexer
C4
10 2
C5
C6
C7
C8
M
PLL Reference
Clock at the
Input Pin
PLL Clock at
the Register
Clock Port
The PLL clock outputs
can lead or lag the fbin
clock input.
Dedicated PLL
Clock Outputs
fbin Clock Input Pin
input pin in this mode. The external
fbin
I/O / FPLL_<#>_CLKOUT0
/ FPLL_<#>_CLKOUTp /
FPLL_<#>_FB
fbout[p]
EXTCLKOUT[0]
fbin
I/O / FPLL_<#>_CLKOUT1 /
FPLL_<#>_ CLKOUTn
fbout[n]
EXTCLKOUT[1]
fbout
I/O /FPLL_<#>_FBp
fbin[p]
I/O / FPLL_<#>_FBn
fbin[n]
Phase Aligned
Clock Networks and PLLs in Cyclone V Devices
CV-52004
2014.01.10
External board connection for one
differential clock output and one
differential feedback input for
differential EFB support.
For differential EFB mode,
FPLL_<#>_CLKOUT[p,n] are the
fbout[p,n] output pin; while
FPLL_<#>_FB[p,n] are the fbin[p,n]
External
input pins.
Board Trace
External board connection for one
single-ended clock output and one
single-ended feedback input for
single-ended EFB support.
For single-ended EFB mode,
FPLL_<#>_CLKOUT1 is the fbout
output pin; while the FPLL_<#>_FB is
the fbin input pin.
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