Clocks - Altera Cyclone V Device Handbook

cv_54011
2013.12.30
Data Transmit
• No CRC status during a write data transfer, if the CRC status start bit is not received for two clock
cycles after the end bit of the data block is sent out, the data path performs the following actions:
• Signals no CRC status error to the BIU
• Terminates further data transfer
• Signals data transfer done to the BIU
• Negative CRC if the CRC status received after the write data block is negative (that is, not 0b010), the
data path signals a data CRC error to the BIU and continues with the data transfer.
• Data starvation due to empty FIFO buffer if the FIFO buffer becomes empty during a write data
transmission, or if the card clock stopped and the FIFO buffer remains empty for a data-timeout number
of clock cycles, the data path signals a data-starvation error to the BIU and the data path continues to
wait for data in the FIFO buffer.
Data Receive
• Data timeout during a read-data transfer, if the data start bit is not received before the number of clock
cycles specified in the timeout register, the data path does the following action:
• Signals a data-timeout error to the BIU
• Terminates further data transfer
• Signals data transfer done to BIU
• Data SBE during a 4-bit or 8-bit read-data transfer, if the all-bit data line does not have a start bit, the
data path signals a data SBE to the BIU and waits for a data timeout, after which it signals that the data
transfer is done.
• Data CRC error during a read-data-block transfer, if the CRC-16 received does not match with the
internally generated CRC-16, the data path signals a data CRC error to the BIU and continues with the
data transfer.
• Data EBE during a read-data transfer, if the end bit of the received data is not 1, the data path signals
an EBE to the BIU, terminates further data transfer, and signals to the BIU that the data transfer is done.
• Data starvation due to FIFO buffer full during a read data transmission and when the FIFO buffer
becomes full, the card clock stops. If the FIFO buffer remains full for a data-timeout number of clock
cycles, the data path signals a data starvation error to the BIU, by setting the data starvation host timeout
bit (hto) in rintsts register to 1, and the data path continues to wait for the FIFO buffer to empty.

Clocks

Table 11-14: SD/MMC Controller Clocks
Clock Name
l4_mp_clk
sdmmc_clk
sdmmc_cclk_out
sdmmc_clk_divided
SD/MMC Controller
Send Feedback
†
†
†
†
†
†
†
†
†
†
Direction
In Clock for SD/MMC controller BIU
In Clock for SD/MMC controller
Out Generated output clock for card
Internal Divide-by-four clock of sdmmc_clk
†
Data Transmit
†
†
Description
Altera Corporation
11-27
†
†
†