Lab Control Signals - Altera Cyclone V Device Handbook

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LAB Control Signals

Figure 1-3: LAB Fast Local and Direct Link Interconnects for Cyclone V Devices
LAB Control Signals
Each LAB contains dedicated logic for driving the control signals to its ALMs, and has two unique clock
sources and three clock enable signals.
The LAB control block generates up to three clocks using the two clock sources and three clock enable
signals. Each clock and the clock enable signals are linked.
De-asserting the clock enable signal turns off the corresponding LAB-wide clock.
Altera Corporation
Direct Link Interconnect from
Left LAB, Memory Block,
DSP Block, or IOE Output
ALMs
Direct Link
Interconnect
to Left
Fast Local
Interconnect
MLAB
Direct Link Interconnect from
Right LAB, Memory Block,
DSP Block, or IOE Output
LAB
Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices
ALMs
Direct Link
Interconnect
to Right
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CV-52001
2014.01.10