Altera Cyclone V Device Handbook page 362

2-24
Selecting a Transmitter Datapath Interface Clock
Figure 2-19: Six Identical Channels with a Single User-Selected Transmitter Interface Clock
To clock six identical channels with a single clock, perform these steps:
1. Instantiate the tx_coreclkin port for all the identical transmitter channels (tx_coreclkin[5:0]).
2. Connect tx_clkout[4] to the tx_coreclkin[5:0] ports.
3. Connect tx_clkout[4] to the transmitter data and control logic for all six channels.
Note: Resetting or powering down channel 4 causes a loss of the clock for all six channels.
The common clock must have a 0 ppm difference for the read side of the transmitter phase compensation
FIFO of all the identical channels. A frequency difference causes the FIFO to under run or overflow, depending
on whether the common clock is slower or faster, respectively.
You can drive the 0 ppm common clock by one of the following sources:
• tx_clkout of any channel in non-bonded channel configurations
• tx_clkout[0] in bonded channel configurations
• Dedicated refclk pins
Note: The Quartus II software does not allow gated clocks or clocks that are generated in the FPGA logic
to drive the tx_coreclkin ports.
You must ensure a 0 ppm difference. The Quartus II software is unable to ensure a 0 ppm difference because
it allows you to use external pins, such as dedicated refclk pins.
Altera Corporation
Transceivers
Channel 7
Channel 6
Channel 5
Channel 4
tx_clkout[4]
Channel 3
Channel 2
Channel 1
Channel 0
FPGA Fabric
tx_coreclkin[7]
tx_coreclkin[6]
tx_coreclkin[5]
tx_coreclkin[4]
Channel [7:0] Transmitter
Data and Control Logic
tx_coreclkin[3]
tx_coreclkin[2]
tx_coreclkin[1]
tx_coreclkin[0]
Transceiver Clocking in Cyclone V Devices
CV-53002
2013.05.06
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