Altera Cyclone V Device Handbook page 197

CV-52006
2014.01.10
Figure 6-11: PHYCLK Networks in Cyclone V SE A2, A4, A5, and A6 Devices
Figure 6-12: PHYCLK Networks in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and D6
Devices
External Memory Interfaces in Cyclone V Devices
Send Feedback
I/O Bank 8
Sub-Bank Sub-Bank
Left
PLL
PHYCLK Networks
FPGA Device
PHYCLK Networks
Left
PLL
Sub-Bank Sub-Bank
I/O Bank 3
I/O Bank 8
Sub-Bank Sub-Bank
Left
PLL
PHYCLK Networks
FPGA Device
PHYCLK Networks
Left
PLL
Sub-Bank Sub-Bank
I/O Bank 3
PHY Clock (PHYCLK) Networks
I/O Bank 7
Sub-Bank Sub-Bank
HPS
PLL
HPS Block
Right
PLL
Sub-Bank Sub-Bank
I/O Bank 4
I/O Bank 7
Sub-Bank Sub-Bank
HPS
PLL
HPS Block
Right
PLL
Sub-Bank Sub-Bank
I/O Bank 4
6-23
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