Clock Frequency Configuration - Altera Cyclone V Device Handbook

20-10

Clock Frequency Configuration

Figure 20-10: Multiple Master Clock Synchronization †
Clock Frequency Configuration
When you configure the I
transaction can take place in order to ensure proper I/O timing. † There are four SCL count registers:
• Standard speed I
• Standard speed I
• Fast speed I
• Fast speed I
It is not necessary to program any of the SCL count registers if the I
2
as an I C slave, since these registers are used only to determine the SCL timing requirements for operation
2
as an I C master. †
Minimum High and Low Counts
2
When the I C controller operates as an I
value that can be programmed in the SCL low count registers is 8 while the minimum value allowed for the
SCL high count registers is 6. †
The minimum value of 8 for the low count registers is due to the time required for the I
SDA after a negative edge of SCL. The minimum value of 6 for the high count register is due to the time
required for the I
2
The I C controller adds one cycle to the low count register values in order to generate the low period of the
SCL clock.
2
The I C controller adds seven cycles to the high count register values in order to generate the high period
of the SCL clock. This is due to the following factors: †
• The digital filtering applied to the SCL line incurs a delay of four l4_sp_clk cycles. This filtering
includes metastability removal and a 2-out-of-3 majority vote processing on SDA and SCL edges. †
• Whenever SCL is driven 1 to 0 by the I
logic latency of three l4_sp_clk cycles incurs. †
Consequently, the minimum SCL low time of which the I
periods (8+1), while the minimum SCL high time is thirteen (13) l4_sp_clk periods (6+1+3+3). †
Altera Corporation
CLKA
CLKB
SCL
SCL Low Transition Resets
All Clocks; Start Counting
Their Low Periods
2
C controller as a master, the SCL count registers must be set before any I
2
C clock SCL high count, IC_SS_SCL_HCNT †
2
C clock SCL low count, IC_SS_SCL_LCNT †
2
C clock SCL high count, IC_FS_SCL_HCNT †
2
C clock SCL low count, IC_FS_SCL_LCNT †
2
C controller to sample SDA during the high period of SCL. †
Wait State Start Counting High Period
SCL Transitions High
When All Clocks Are in a High State
2
C master in both transmit and receive transfers, the minimum
2
C controller that is, completing the SCL high time an internal
2
C controller is capable is nine (9) l4_sp_clk
2
C controller is enabled to operate only
2
C controller to drive
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cv_54020
2013.12.30
2
C bus
I2C Controller