Lightweight Hps-To-Fpga Bridge - Altera Cyclone V Device Handbook

5-10

Lightweight HPS-to-FPGA Bridge

Signal
1 bit
RVALID
1 bit
RREADY
Lightweight HPS-to-FPGA Bridge
The lightweight HPS-to-FPGA bridge provides a lower-performance interface to the FPGA fabric. This
interface is useful for accessing the control and status registers of soft peripherals. The bridge provides a
2 MB address space and access to logic, peripherals, and memory implemented in the FPGA fabric. The
MPU subsystem, direct memory access (DMA) controller, and debug access port (DAP) can use the lightweight
HPS-to-FPGA bridge to access the FPGA fabric or GPV. Master interfaces in the FPGA fabric can also use
the lightweight HPS-to-FPGA bridge to access the GPV registers in all three bridges.
The bridge master exposed to the FPGA fabric has a fixed data width of 32 bits. The slave interface of the
bridge in the HPS logic has a fixed data width of 32 bits.
Use the lightweight HPS-to-FPGA bridge as a secondary, lower-performance master interface to the FPGA
fabric. With a fixed width and a smaller address space, the lightweight bridge is useful for low-bandwidth
traffic, such as memory-mapped register accesses to FPGA peripherals. This approach diverts traffic from
the high-performance HPS-to-FPGA bridge, and can improve both CSR access latency and overall system
performance.
The following table lists the properties of the lightweight HPS-to-FPGA bridge, including the master interface
exposed to the FPGA fabric.
Table 5-15: Lightweight HPS-to-FPGA Bridge Properties
Bridge Property
Data width
Clock domain
Byte address width
ID width
Read acceptance
Write acceptance
Total acceptance
The lightweight HPS-to-FPGA bridge has three master interfaces, as shown in AXI Bridges Block Diagram
and System Integration. The master interface connected to the FPGA fabric provides a lightweight interface
from the HPS to custom logic in the FPGA fabric. The two other master interfaces, connected to the HPS-
to-FPGA and FPGA-to-HPS bridges, allow you to access the GPV registers for each bridge.
The lightweight HPS-to-FPGA bridge also has a GPV to control the behavior of its four interfaces (one slave
and three masters). The GPV is described in The Global Programmers View.
Altera Corporation
Width Direction
Input
Output
L3 Slave Interface
32 bits
l4_mp_clk
32 bits
12 bits
16 transactions
16 transactions
32 transactions
Description
Read data channel valid
Read data channel ready
32 bits
h2f_lw_axi_clk
21 bits
12 bits
16 transactions
16 transactions
32 transactions
2013.12.30
FPGA Master Interface
HPS-FPGA AXI Bridges
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