Altera Cyclone V Device Handbook page 856

cv_54017
2013.12.30
Signal Name
phy_rxdv_i
phy_rxer_i
rst_clk_rx_n_o
phy_crs_i
phy_col_i
gmii_mdi_i
gmii_mdo_o
gmii_mdo_o_e
Ethernet Media Access Controller
Send Feedback
In/Out Width
In 1
In 1
Out 1
In 1
In 1
In 1
Out 1
Out 1
EMAC to FPGA PHY Interface
Description
PHY Receive Data Valid. This signal is driven
by PHY and has multiple functions depending
on which PHY interface is selected, as listed
below:
• GMII: When high, indicates that the data
on the phy_rxd bus is valid. It remains
asserted continuously from the first
recovered byte of the frame through the final
recovered byte. Synchronous to:
phy_ clk_rx_i
• RGMII: This is the receive control signal
(RX_CTL) used to qualify the data received
on phy_rxd. On the rising edge of the clock,
rxdv is sampled. On the falling edge of the
clock, rxdv XOR rxerr is sampled.
Synchronous to: phy_clk_rx_i, both rising
and falling edges.
PHY Receive Error. This signal is driven by the
PHY. In GMII / MII mode, it indicates an error
or carrier extension (GMII) in the received
frame. Synchronous to: phy_clk_rx_i, This
signal is not used in RGMII mode.
Receive clock reset output.
PHY Carrier Sense. This signal, valid only in
the GMII / MII mode, is asserted by the PHY
when either the transmit or receive medium is
not idle. The PHY de-asserts this signal when
both transmit and receive medium are idle. This
signal is not synchronous to any clock.
PHY Collision Detect. This signal, valid only
in GMII / MII mode operating in half duplex,
is asserted by the PHY when a collision is
detected on the medium. This signal is not
synchronous to any clock.
MDIO signal input. This signal is driven
synchronously with the gmii_mdc_o clock.
MDIO signal data out. This signal is driven
synchronously with the gmii_mdc_o clock.
MDIO signal output enable. This signal is
driven synchronously with the gmii_mdc_o
clock.
17-7
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