Altera Cyclone V Device Handbook page 448

Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual
FPGA Manager Building Blocks..................................................................................................13-3
FPGA Configuration.....................................................................................................................13-4
Clock................................................................................................................................................13-7
Reset.................................................................................................................................................13-8
FPGA Manager Address Map and Register Definitions......................................................................13-8
Document Revision History.....................................................................................................................13-8
System Manager.................................................................................................14-1
Features of the System Manager..............................................................................................................14-1
System Manager Block Diagram and System Integration....................................................................14-2
Functional Description of the System Manager....................................................................................14-3
Boot Configuration and System Information............................................................................14-3
Additional Module Control..........................................................................................................14-3
FPGA Interface Enables................................................................................................................14-6
ECC and Parity Control................................................................................................................14-7
Preloader Handoff Information...................................................................................................14-7
Clocks..............................................................................................................................................14-8
Resets...............................................................................................................................................14-8
System Manager Address Map and Register Definitions.....................................................................14-8
Document Revision History.....................................................................................................................14-8
Scan Manager.....................................................................................................15-1
Features of the Scan Manager..................................................................................................................15-1
Scan Manager Block Diagram and System Integration........................................................................15-2
Functional Description of the Scan Manager........................................................................................15-5
Configuring HPS I/O Scan Chains..............................................................................................15-5
Communicating with the JTAG TAP Controller......................................................................15-6
JTAG-AP FIFO Buffer Access and Byte Command Protocol.................................................15-6
Clocks..............................................................................................................................................15-7
Resets...............................................................................................................................................15-7
Scan Manager Address Map and Register Definitions.........................................................................15-8
JTAG-AP Register Name Cross Reference Table..................................................................................15-8
Document Revision History.....................................................................................................................15-9
DMA Controller................................................................................................16-1
Features of the DMA Controller..............................................................................................................16-1
DMA Controller Block Diagram and System Integration...................................................................16-3
TOC-9
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