Altera Cyclone V Device Handbook page 537

5-6
FPGA-to-HPS Bridge Slave Signals
Table 5-6: FPGA-to-HPS Bridge Slave Write Response Channel Signals
Signal
8 bits
BID
2 bits
BRESP
1 bit
BVALID
1 bit
BREADY
Table 5-7: FPGA-to-HPS Bridge Slave Read Address Channel Signals
Signal
8 bits
ARID
32 bits
ARADDR
4 bits
ARLEN
3 bits
ARSIZE
2 bits
ARBURST
2 bits
ARLOCK
4 bits
ARCACHE
3 bits
ARPROT
1 bit
ARVALID
1 bit
ARREADY
5 bits
ARUSER
Table 5-8: FPGA-to-HPS Bridge Slave Read Data Channel Signals
Signal
8 bits
RID
32, 64, or 128 bits
RDATA
2 bits
RRESP
1 bit
RLAST
1 bit
RVALID
1 bit
RREADY
Altera Corporation
Width Direction
Output
Output
Output
Input
Width Direction
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Width Direction
Output
Output
Output
Output
Output
Input
Description
Write response ID
Write response
Write response channel valid
Write response channel ready
Description
Read address ID
Read address
Burst length
Burst size
Burst type
Lock type Valid values are 00 (normal access) and
01 (exclusive access)
Cache policy type
Protection type
Read address channel valid
Read address channel ready
Read user sideband signals
Description
Read ID
Read data
Read response
Read last data identifier
Read data channel valid
Read data channel ready
cv_54005
2013.12.30
HPS-FPGA AXI Bridges
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