Altera Cyclone V Device Handbook page 965

20-14
Slave-Transmitter Operation for a Single Byte
Note: Slaves and masters do not have to be programmed with the same type of addressing 7- or 10-bit
address. For instance, a slave can be programmed with 7-bit addressing and a master with 10-bit
addressing, and vice versa. †
4. Enable the I
Slave-Transmitter Operation for a Single Byte
When another I
acts as a slave-transmitter and the following steps occur: †
1. The other I
the IC_SAR register of the I
2
2. The I C controller acknowledges the sent address and recognizes the direction of the transfer to indicate
that it is acting as a slave-transmitter. †
2
3. The I C controller asserts the RD_REQ interrupt (bit 5 of the IC_RAW_INTR_STAT register) and waits
for software to respond. †
If the RD_REQ interrupt has been masked, due to bit 5 of the IC_INTR_MASK register (M_RD_REQ bit
field) being set to 0, then it is recommended that you instruct the CPU to perform periodic reads of the
IC_RAW_INTR_STAT register. †
• Reads that indicate bit 5 of the IC_RAW_INTR_STAT register (R_RD_REQ bit field) being set to 1
must be treated as the equivalent of the RD_REQ interrupt being asserted. †
• Software must then act to satisfy the I
• The timing interval used should be in the order of 10 times the fastest SCL clock period the I
controller can handle. For example, for 400 Kbps, the timing interval is 25 us. †
Note: The value of 10 is recommended here because this is approximately the amount of time required
for a single byte of data transferred on the I
4. If there is any data remaining in the TX FIFO before receiving the read request, the I
a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register) to flush the old data from the TX
FIFO. †
Note: Because the I
event occurs, it is necessary for software to release the I
the IC_CLR_TX_ABRT register before attempting to write into the TX FIFO. For more
information, refer to the C_RAW_INTR_STAT register description in the register map.†
If the TX_ABRT interrupt has been masked, due to of IC_INTR_MASK[6] register (M_TX_ABRT bit
field) being set to 0, then it is recommended that the CPU performs periodic reads of the
IC_RAW_INTR_STAT register. †
• Reads that indicate bit 6 (R_TX_ABRT) being set to 1 must be treated as the equivalent of the TX_ABRT
interrupt being asserted. †
• There is no further action required from software. †
• The timing interval used should be similar to that described in the previous step for the
IC_RAW_INTR_STAT[5] register. †
5. Software writes to the DAT bits of the IC_DATA_CMD register with the data to be written and writes a
0 in bit 8.†
6. Software must clear the RD_REQ and TX_ABRT interrupts (bits 5 and 6, respectively) of the
IC_RAW_INTR_STAT register before proceeding. †
Altera Corporation
2
C controller by writing a 1 in bit 0 of the IC_ENABLE register. †
2
C master device on the bus addresses the I
2
C master device initiates an I
2
C controller †
2
C controller's TX FIFO is forced into a flushed/reset state whenever a TX_ABRT
2
C controller and requests data, the I
2
C transfer with an address that matches the slave address in
2
C transfer. †
2
C bus.†
2
C controller from this state by reading
cv_54020
2013.12.30
2
C controller
2
C
2
C controller asserts
I2C Controller
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