Usb Otg Controller Programming Model; Enabling Spram Eccs; Host Operation - Altera Cyclone V Device Handbook

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USB OTG Controller Programming Model

USB OTG Controller Programming Model
For detailed information about using the USB OTG controller, consult your operating system (OS) driver
documentation. The OS vendor provides application programming interfaces (APIs) to control USB host,
device and OTG operation. This section provides a brief overview of the following software operations:

• Enabling SPRAM ECCs

• Host operation

• Device operation
Enabling SPRAM ECCs
To avoid false ECC errors, you must initialize the ECC bits in the SPRAM before using ECCs. To initialize
the ECC bits, software writes data to all locations in the SPRAM.
The L3 interconnect has access to the SPRAM is accessible through the USB OTG L3 slave interface. Software
accesses the SPRAM through the directfifo memory space, in the USB OTG controller address space.
The SPRAM contains 8192 (32 KB) locations. The L3 slave provides 32-bit access to the SPRAM. Physically
the SPRAM is implemented as a 35-bit memory, with the highest three bits reserved for the USB OTG
controller's internal use. When a write is performed to the SPRAM through the L3 slave interface, bits 32
through 34 of the internal data bus are tied to 1, to enable the ECC bits to be initialized.
Note: Software cannot access the SPRAM beyond the 32-KB range. Out-of-range read transactions return
indeterminate data. Out-of-range write transactions are ignored.
Related Information
USB OTG Controller Address Map and Register Definitions
The directfifo memory space is described in the controller address map.
Host Operation
Host Initialization
After power up, the USB port is in its default mode. No VBUS is applied to the USB cable. The following
process sets up the USB OTG controller as a USB host.
1. To enable power to the USB port, the software driver sets the Port Power (prtpwr) bit to 1 in the Host
Port Control and Status Register (hprt) of the Host Mode Registers (hostgrp) group. This action
drives the V
The controller waits for a connection to be detected on the USB link.
2. When a USB device connects, an interrupt is generated. The Port Connect Detected (PrtConnDe t)
bit in hprt is set to 1.
3. Upon detecting a port connection, the software driver initiates a port reset by setting the Port Reset
(prtrst) bit to 1 in hprt.
4. The software driver must wait a minimum of 10 ms so that speed enumeration can complete on the USB
link.
5. After the 10 ms, the software driver sets prtrst back to 0 to release the port reset.
6. The USB OTG controller generates an interrupt. The Port Enable Disable Change (prtenchng) and
Port Speed (prtspd) bits, in hprt, are set to reflect the enumerated speed of the device that attached.
Altera Corporation
signal on the USB link.
BUS
on page 18-15
USB 2.0 OTG Controller
cv_54018
2013.12.30
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