Altera Cyclone V Device Handbook page 979

21-6
Programmable THRE Interrupt
Figure 21-4: Programmable THRE Interrupt
The threshold level is programmed into IIR_FCR.TET. The available empty thresholds are empty, 2, ¼,
and ½. The optimum threshold value depends on the system's ability to begin a new transmission sequence
in a timely manner. However, one of these thresholds should prove optimum in increasing system performance
by preventing the transmit FIFO buffer from running empty.
In addition to the interrupt change, line status register (LSR.THRE) also switches from indicating that the
transmit FIFO buffer is empty, to indicating that the FIFO buffer is full. This change allows software to fill
the FIFO buffer for each transmit sequence by polling LSR.THRE before writing another character. This
directs the UART to fill the transmit FIFO buffer whenever an interrupt occurs and there is data to transmit,
instead of waiting until the FIFO buffer is completely empty. Waiting until the FIFO buffer is empty reduces
performance whenever the system is too busy to respond immediately. You can increase system efficiency
when this mode is enabled in combination with automatic flow control.
When not selected or disabled, THRE interrupts and LSR.THRE function normally, reflecting an empty
THR or FIFO buffer.
Altera Corporation
Clear INTR
yes
FIFO Level > TX
Empty Trigger?
no
no
THRE Interrupt
Enabled?
yes
Set INTR
no
FIFO Level > TX
Empty Trigger?
yes
cv_54021
2013.12.30
UART Controller
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