Altera Cyclone V Device Handbook page 504

3-8
Module Reset Signals
Module Reset Signal
sys_manager_cold_rst_n
fpga_manager_rst_n
acp_id_mapper_rst_n
h2f_rst_n
h2f_cold_rst_n
rst_pin_rst_n
timestamp_cold_rst_n
clk_manager_cold_rst_n
scan_manager_rst_n
frz_ctrl_cold_rst_n
sys_dbg_rst_n
dbg_rst_n
tap_cold_rst_n
sdram_cold_rst_n
Altera Corporation
Description
Resets system manager
(resets logic associated with
cold reset only)
Resets FPGA manager
Resets ACP ID mapper
Resets user logic in FPGA
fabric (resets logic
associated with cold or
warm reset)
Resets user logic in FPGA
fabric (resets logic
associated with cold reset
only)
Pulls nRST pin low
Resets debug timestamp to
0x0
Resets clock manager
(resets logic associated with
cold reset only)
Resets scan manager
Resets freeze controller
(resets logic associated with
cold reset only)
Resets debug masters and
slaves connected to L3
interconnect and level 4
(L4) buses
Resets debug components
including DAP, trace, MPU
debug logic, and any user
debug logic in the FPGA
fabric
Resets portion of TAP
controller in the DAP that
must be reset on a cold reset
Resets SDRAM subsystem
(resets logic associated with
cold reset only)
Reset Cold Warm
Domain Reset Reset
System X
System X X
System X X
System X X
System X
System X X
System X
System X
System X X
System X
System X X
Debug X
TAP X
System X X
cv_54003
2013.12.30
Debug Software
Reset Deassert
X
Reset Manager
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