Altera Cyclone V Device Handbook page 539

5-8
HPS-to-FPGA Bridge Master Signals
Related Information
• The Global Programmers View
• GPV Clocks
• Cortex-A9 Microprocessor Unit Subsystem
For details about L2 cache address filtering, refer to the Cortex-A9 Microprocessor Unit Subsystem chapter.
HPS-to-FPGA Bridge Master Signals
All the HPS-to-FPGA bridge master signals have a fixed width except the data and write strobes for the read
and write data channels. The variable-width signals depend on the data width setting of the bridge interface
exposed to the FPGA logic. The following tables list all the signals exposed by the HPS-to-FPGA master
interface to the FPGA fabric.
Table 5-10: HPS-to-FPGA Bridge Master Write Address Channel Signals
Signal
12 bits
AWID
30 bits
AWADDR
4 bits
AWLEN
3 bits
AWSIZE
2 bits
AWBURST
2 bits
AWLOCK
4 bits
AWCACHE
3 bits
AWPROT
1 bit
AWVALID
1 bit
AWREADY
Table 5-11: HPS-to-FPGA Bridge Master Write Data Channel Signals
Signal
WID
WDATA
WSTRB
WLAST
WVALID
Altera Corporation
on page 5-3
on page 5-14
Width Direction
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Width Direction
12 bits Output
32, 64, or 128 Output
bits
4, 8, or 16 bits Output
1 bit Output
1 bit Output
on page 6-1
Description
Write address ID
Write address
Burst length
Burst size
Burst type
Lock type Valid values are 00 (normal access) and
01 (exclusive access)
Cache policy type
Protection type
Write address channel valid
Write address channel ready
Write ID
Write data
Write data strobes
Write last data identifier
Write data channel valid
Description
HPS-FPGA AXI Bridges
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2013.12.30