Receiver Pcs Datapath - Altera Cyclone V Device Handbook

1-34

Receiver PCS Datapath

Table 1-15: Bits Slip Allowed with the tx_bitslipboundaryselect signal
Operation Mode
Single width (8 or 10 bit)
Double width (16 or 20 bit)
Receiver PCS Datapath
The sub-blocks in the receiver PCS datapath are described in order from the word aligner to the receiver
phase compensation FIFO block.
Table 1-16: Blocks in the Receiver PCS Datapath
Block
Word Aligner
Rate Match FIFO
8B/10B Decoder
Byte Deserializer
Byte Ordering
Altera Corporation
9
19
• Searches for a predefined alignment pattern in the deserialized data to
identify the correct boundary and restores the word boundary during
link synchronization
• Supports an alignment pattern length of 7, 8, 10, 16, 20, or 32 bits
• Supports operation in four modes—manual alignment, bit-slip,
automatic synchronization state machine, and deterministic latency
state machine—in single- and double-width configurations
• Supports the optional programmable run-length violation detection,
polarity inversion, bit reversal, and byte reversal features
• Compensates for small clock frequency differences of up to ±300 parts
per million (ppm)—600 ppm total—between the upstream transmitter
and the local receiver clocks by inserting or deleting skip symbols when
necessary
• Supports operation that is compliant to the clock rate compensation
function in supported protocols
• Receives 10-bit data and decodes the data into an 8-bit data and a 1-
bit control identifier—in compliance with Clause 36 of the IEEE 802.3
specification
• Supports operation in single- and double-width modes
• Halves the FPGA fabric transceiver interface frequency at the receiver
channel by doubling the receiver output datapath width
• Allows the receiver channel to operate at higher data rates with the
FPGA fabric transceiver interface frequency that is within maximum
limit
• Supports operation in single- and double-width modes
• Searches for a predefined pattern that must be ordered to the LSByte
position in the parallel data going to the FPGA fabric when you enable
the byte deserializer
Maximum Bit-Slip Setting
Functionality
Transceiver Architecture in Cyclone V Devices
CV-53001
2013.05.06
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