Altera Cyclone V Device Handbook page 346

2-8
Transmitter Clock Network
Figure 2-7: x6 and xN Clock Line Architecture
The x6 clock lines are driven by serial and parallel clocks from the central clock divider in channels 1 and
4. For channels 0 to 5 within the 2 transceiver banks, the serial and parallel clocks in the x6 clock line are
then distributed to every channel in both the transceiver banks.
The xN clock lines extend the clocking reach of the x6 clock line to all channels on the same side of the
device. To reach a xN clock line, the clocks must be provided on the x6 clock line. The serial and parallel
clocks in the x6 clock line are distributed to every channel within the two transceiver banks. The serial and
parallel clocks are distributed to other channels beyond the two banks or the six channels using the xN clock
line.
In bonded configurations, serial and parallel clocks from the x6 or xN clock lines are received by the clock
divider of every bonded channel and fed directly to the serializer. In a non-bonded configuration, the clock
divider of every non-bonded channel receives the serial clock from the x6 or xN clock lines and generates
the individual parallel clock to the serializer.
Note: In a bonded configuration, bonded channels must be placed contiguously without leaving a gap
between the channels, except when the gap channel is a CMU PLL used for the bonded channels.
Altera Corporation
CH5 Local Clock Divider
CH4 Central Clock
CH3 Local Clock Divider
CH2 Local Clock Divider
CH1 Central Clock
CH0 Local Clock Divider
CH5 Local Clock Divider
CH4 Central Clock
CH3 Local Clock Divider
CH2 Local Clock Divider
CH1 Central Clock
CH0 Local Clock Divider
Note: All the clock lines shown in this figure carry both the serial and parallel clocks.
x6_top x6_bot xN_top xN_bot
xN_top
xN_bot
x6_top x6_bot
xN_top xN_bot
Transceiver Clocking in Cyclone V Devices
CV-53002
2013.05.06
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