Variable Precision Dsp Blocks In Cyclone V Devices; Features - Altera Cyclone V Device Handbook

Variable Precision DSP Blocks in Cyclone V Devices

2014.01.10
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This chapter describes how the variable-precision digital signal processing (DSP) blocks in Cyclone V devices
are optimized to support higher bit precision in high-performance DSP applications.
Related Information
Cyclone V Device Handbook: Known Issues
Lists the planned updates to the Cyclone V Device Handbook chapters.

Features

The Cyclone V variable precision DSP blocks offer the following features:
High-performance, power-optimized, and fully registered multiplication operations
9-bit, 18-bit, and 27-bit word lengths
Two 18 x 19 complex multiplications
Built-in addition, subtraction, and dual 64-bit accumulation unit to combine multiplication results
Cascading 19-bit or 27-bit to form the tap-delay line for filtering applications
Cascading 64-bit output bus to propagate output results from one block to the next block without external
logic support
Hard pre-adder supported in 19-bit, and 27-bit mode for symmetric filters
Internal coefficient register bank for filter implementation
18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder
Related Information
Cyclone V Device Overview
Provides more information about the number of multipliers in each Cyclone V device.
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