Altera Cyclone V Device Handbook page 397

CV-53004
2013.10.17
Two flags are forwarded to the FPGA fabric:
• rx_rmfifodatadeleted - Asserted for two clock cycles for each deleted /I2/ ordered set to indicate
the rate match FIFO deletion event
• rx_rmfifodatainserted - Asserted for two clock cycles for each inserted /I2/ ordered set to indicate
the rate match FIFO insertion event
For more information about the rate match FIFO, refer to the
Devices chapter.
GbE Protocol-Ordered Sets and Special Code Groups
Table 4-5: GIGE Ordered Sets
The following ordered sets and special code groups are specified in the IEEE 802.3-2008 specification.
Code
/C/
/C1/
/C2/
/I/
/I1/
/I2/
-
/R/
/S/
/T/
/V/
Table 4-6: Synchronization State Machine Parameters in GbE Mode
Synchronization State Machine Parameters
Number of valid {/K28.5/, /Dx,y/} ordered sets received to achieve
synchronization
Number of errors received to lose synchronization
Number of continuous good code groups received to reduce the error
count by 1
(12)
Two data code groups represent the Config_Reg value.
Transceiver Protocol Configurations in Cyclone V Devices
Send Feedback
Ordered Set
Configuration
Configuration 1
Configuration 2
IDLE
IDLE 1
IDLE 2
Encapsulation
Carrier_Extend
Start_of_Packet
End_of_Packet
Error_Propagation
Gigabit Ethernet Transceiver Datapath
Transceiver Architecture for Cyclone V
Number of Code
Groups
— Alternating /C1/ and /C2/
4
/K28.5/D21.5/ Config_Reg
(12)
4 /K28.5/D2.2/ Config_Reg
— Correcting /I1/, Preserving /I2/
2 /K28.5/D5.6/
2 /K28.5/D16.2/
— —
1 /K23.7/
1 /K27.7/
1 /K29.7/
1 /K30.7/
4-15
Encoding
Setting
3
4
4
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