Transceiver Clocking And Channel Placement Guidelines In Xaui Configuration - Altera Cyclone V Device Handbook

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Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration

Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration
Transceiver Clocking
Figure 4-21: Transceiver Clocking for XAUI Configuration
One of the two channel PLLs configured as a CMU PLL in a transceiver bank generates the transmitter serial
and parallel clocks for the four XAUI channels. The x6 clock line carries the transmitter clocks to the PMA
and PCS of each of the four channels.
Channel 3
Channel 2
Channel 1
Channel 0
16
xgmii_tx_clk
16
xgmii_rx_clk
Parallel Clock
Table 4-7: Input Reference Clock Frequency and Interface Speed Specifications for XAUI Configurations
Input Reference Clock Frequency
(MHz)
156.25
Transceiver Clocking Guidelines for Soft PCS Implementation
In the soft PCS implementation in the XAUI configuration, you must route xgmii_rx_clk to
xgmii_tx_clk as shown in the following figure.
This method uses xgmii_rx_clk to compensate for the phase difference on the TX side.
Without this method, the tx_digitalreset signal may experience intermittent failure.
Altera Corporation
FPGA Fabric
Soft PCS
Soft PCS
Soft PCS
Soft PCS
20
20
Parallel Clock
(Recovered) from Channel 0
CMU PLL
Serial Clock
(From the ×1 Clock Lines)
FPGA Fabric-Transceiver Interface Width
16-bit data, 2-bit control
Channel 3 Transmitter Standard PCS
Channel 2 Transmitter Standard PCS
Channel 1 Transmitter Standard PCS
Channel 0 Transmitter Standard PCS
20
/2
Receiver Standard PCS
20
/2
Parallel Clock (Recovered)
Central/ Local Clock Divider
Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
FPGA Fabric-Transceiver Interface
156.25
Transceiver Protocol Configurations in Cyclone V Devices
Transmitter PMA Ch 3
Transmitter PMA Ch 2
Transmitter PMA Ch 1
Transmitter PMA Ch 0
10
Parallel Clock
Receiver PMA
10
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Frequency (MHz)
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CV-53004
2013.10.17