Altera Cyclone V Device Handbook page 675

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2013.12.30
3. Write 0x1000 to the Data register.
4. Write to the command register, setting the CMD_MAP field to 2 and the BLK_ADDR field to the starting
address of the new area to be written. This address must also be plane-aligned.
5. Write 0x11<PP> to the Data register, where <PP> is the number of pages to copy.
The parameter <PP> must be a multiple of the number of planes in the device.
Pipeline Read-Ahead and Write-Ahead Operations
The NAND flash controller supports pipeline read-ahead and write-ahead operations. However, the flash
device might have limited support for this function. If the device does not support pipeline read-ahead or
write-ahead, the flash controller processes these commands as standard reads or writes.
The NAND flash controller can handle at the most four outstanding pipeline commands, queued up in the
order in which the flash controller received the commands. The flash controller operates on the pipeline
command at the head of the queue until all the pages corresponding to the pipeline command are executed.
The flash controller then pops the pipeline command at the head of the queue and proceeds to work on the
next pipeline command in the queue.
The pipeline read-ahead function allows for a continuous reading of the flash memory. On receiving a
pipeline read command, the flash controller immediately issues a load command to the device. While data
is read out with MAP01 commands in a consecutive or multi-plane address pattern, the flash controller
maintains additional cache or multi-plane read command sequencing for continuous streaming of data from
the flash device.
The pipeline write-ahead function allows for a continuous writing of the flash memory. While data is written
with MAP01 commands in a consecutive or multi-plane address pattern, the NAND flash controller maintains
cache or multi-plane command sequences for continuous streaming of data into the flash device.
MAP01 commands must read or write pages in the same sequence that the pipelined commands were issued
to the NAND flash controller. If the host issues multiple pipeline commands, pages must be read or written
in the order the pipeline commands were issued. It is not possible to read or write pages for a second pipeline
command before completing the first pipeline command. If the pipeline sequence is broken by a MAP01
command, the pipe_cmd_err interrupt is issued, and the flash controller clears the pipeline command
queue. The flash controller services the violating incoming MAP01 read or write request with a normal page
read or write sequence.
For a multi-plane device that supports multi-plane programming, you must set the flag bit of the
multiplane_operation register in the config group to 1. In this case, the data is interleaved into
page-size chunks to consecutive blocks.
Pipeline read-ahead commands can read data from the queue in this interleaved fashion. The parameter
<PP> denotes the total number of pages in multiples of the number of planes available, and the block address
must be plane-aligned, which keeps the page address constant while incrementing the block address for each
page-size chunk of data. After reading from every plane, the NAND flash controller increments the page
address and resets the block address to the initial address. You can also use pipeline write-ahead commands
in multi-plane mode. The write operation works similarly to the read operation, holding the page address
constant while incrementing the block address until all planes are written.
Note: The same four-entry queue is used to queue the address and page count for pipeline read-ahead and
write-ahead commands. This commonality requires that you use MAP01 commands to read out all
pages for a pipeline read-ahead command before the next pipeline command can be processed.
NAND Flash Controller
Send Feedback
Pipeline Read-Ahead and Write-Ahead Operations
10-37
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