Ddr Phy; Clocks - Altera Cyclone V Device Handbook

8-16

DDR PHY

DDR PHY
The DDR PHY connects the memory controller and external memory devices in the speed critical command
path.
The DDR PHY implements the following functions:
• Calibration the DDR PHY supports the JEDEC-specified steps to synchronize the memory timing
between the controller and the SDRAM chips. The calibration algorithm is implemented in software.
• Memory device initialization the DDR PHY performs the mode register write operations to initialize
the devices. The DDR PHY handles re-initialization after a deep power down.
• Single-data-rate to double-data-rate conversion.

Clocks

All clocks are assumed to be asynchronous with respect to the ddr_dqs_clk memory clock. All transactions
are synchronized to memory clock domain.
Table 8-7: SDRAM Controller Subsystem Clock Domains
Clock Name
ddr_dq_clk
ddr_dqs_clk
ddr_2x_dqs_clk
l4_sp_clk
mpu_l2_ram_clk
l3_main_clk
f2h_sdram_
clk[5:0]
In terms of clock relationships, the FPGA fabric connects the appropriate clocks to write data, read data,
and command ports for the constructed ports.
Related Information
Clock Manager
Altera Corporation
Clock for PHY
Clock for MPFE, single-port controller, CSR access, and PHY
Clock for PHY
Clock for CSR interface
Clock for MPU interface
Clock for L3 interface
Six separate clocks used for the FPGA-to-HPS SDRAM ports to the FPGA
fabric
on page 2-1
Description
SDRAM Controller Subsystem
cv_54008
2013.12.30
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