Altera Cyclone V Device Handbook page 323

1-36
Word Aligner in Manual Alignment Mode
PMA-PCS Interface Width
(bits)
10
16
20
Word Aligner in Manual Alignment Mode
In manual alignment mode, word alignment is manually controlled with the rx_enapatternalign
register. Depending on the configuration, controlling the rx_enapatternalign register enables the
word aligner to look for the predefined word alignment pattern in the received data stream and automatically
synchronizes to the new word boundary.
Altera Corporation
Word Alignment Word Alignment
Mode Pattern Length (bits)
Manual 7 and 10
Alignment
Bit-Slip 7 and 10
Automatic 7 and 10
Synchronized
State Machine
Deterministic 10
Latency State
Machine
Manual 8, 16, and 32
Alignment
Bit-Slip 8, 16, and 32
Manual 7, 10, and 20
Alignment
Bit-Slip 7, 10, and 20
Deterministic 10 and 20
Latency State
Machine
Word Alignment Behavior
User-controlled signal starts the alignment
process. Alignment happens once unless
the signal is reasserted.
User-controlled signal shifts data one bit at
a time.
Data is required to be 8B/10B encoded.
Aligns to selected word aligner pattern
when pre-defined conditions are satisfied.
User-controlled signal starts the alignment
process. After the pattern is found and the
word boundary is identified, the state
machine controls the deserializer to clock-
slip the boundary-indicated number of
serial bits.
Alignment happens automatically after RX
PCS reset. User-controlled signal starts the
alignment process thereafter. Alignment
happens once unless the signal is reasserted.
User-controlled signal shifts data one bit at
a time.
Alignment happens automatically after RX
PCS reset. User-controlled signal starts the
alignment process thereafter. Alignment
happens once unless the signal is reasserted.
User-controlled signal shifts data one bit at
a time.
User-controlled signal starts the alignment
process. After the pattern is found and the
word boundary is identified, the state
machine controls the deserializer to clock-
slip the boundary-indicated number of
serial bits.
Transceiver Architecture in Cyclone V Devices
CV-53001
2013.05.06
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