Altera Cyclone V Device Handbook page 659

cv_54010
2013.12.30
Command Flags Field Description
Bits
14:12 Transfer Mode
11 Reserved
10 Reserved
9 Cont
8 Int
7:0 Burst length
Related Information
Command Descriptor Fields
Status Fields
Bits
15 Complete
14 Fail
13:12 Reserved
NAND Flash Controller
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Name
Sets the transfer mode for the current descriptor.
The encoding is:
• 000 - Default access mode, which uses access settings from the
transfer_spare_reg register
• 001 - Transfer Main and Spare area of data.
• 010 - Transfer only spare area of data.
Other values are reserved.
Must be set to 0
Must be set to 0
The next descriptor address field is valid and descriptor processing should
continue. This bit should be zero only for the last descriptor in a chain.
An interrupt should be issued after the completion of descriptor
processing. The issued interrupt is desc_comp_channel<x> for
channel <x>.
For data DMA commands, this specifies the burst length, in bytes, to be
used on the system bus for transfer of data from or to system memory.
Valid values depend on the host data bus width. Typically, single, 4-beat,
8-beat, and 16-beat bursts are supported. For example, for 32-bit data
bus, the valid values are 4, 16, 32 and 64 bytes.
on page 10-20
Name
When set, denotes that controller has updated status information and
the operation is complete. This bit shall be set even if the operation ended
in a failure. This bit should be in cleared state while descriptor is
constructed. If this bit is set when the controller reads the descriptor for
execution, the controller skips execution of the descriptor and continues
with execution of further descriptors in the chain, depending on the state
of the Continue bit.
When set, denotes that operation failed to complete successfully.
Reserved
Command Flags Field Description
Description
Description
10-21
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