Command Dma - Altera Cyclone V Device Handbook

10-16

Command DMA

MAP10 commands in INCR4 format are written to the Data register at offset 0x10 in nanddata, the same
as MAP10 commands in multitransaction format (described in Multitransaction DMA Command).
Table 10-8: MAP10 Burst DMA (INCR4) Command Structure
Data Beat 15 14
Beat 0 0x2
Beat 1 Memory address high
(25)
Beat 2 Memory address low
(25)
Beat 3 0x0
You can optionally send the 16-bit fields in the above table to the NAND flash controller as four separate
bursts of length 1 in sequential order. Altera recommends this method.
If you want the NAND flash controller DMA to perform cacheable accesses then you must configure the
cache bits by writing the l3master register in the nandgrp group in the system manager. The NAND
flash controller DMA must be idle before you use the system manager to modify its cache capabilities.
Related Information
• Multitransaction DMA Command
• MAP10 Address Mapping
• System Manager
Command DMA
The flash controller supports command DMA, which provides descriptor-based command processing. Each
command descriptor performs one distinct operation on the flash controller. The host software can chain
these command descriptors sequentially as a linked-list of command descriptors and initiate command
DMA to operate on the descriptor chain. The DMA controller fetches a descriptor, carres out the operation
as described in the descriptor, writes the status of the operation completed, generates an interrupt if required,
and fetches the next descriptor. The host is not required to monitor the status of the issued commands,
because the DMA controller updates the status as part of the descriptor fields upon command completion.
The flash controller can support up to four command DMA channels simultaneously. When host software
starts all the command DMA channels in parallel, each channel processes one descriptor at a time from its
list of descriptors.
(25)
The buffer address in host memory, which must be aligned to 32 bits
(26)
INT specifies the host interrupt to be generated at the end of the complete DMA transfer. INT controls the
value of the dma_cmd_comp bit of the intr_status0 register in the status group at the end of the
DMA transfer. INT can take on one of the following values:
0 Do not interrupt host. The dma_cmd_comp bit is set to 0.
1 Interrupt host. The dma_cmd_com p bit is set to 1.
Altera Corporation
13 12 11 10
0x0: read. 0x1: write.
on page 10-13
on page 10-10
on page 14-1
9 8 7 6
<PP>=number of pages
(26)
INT Burst length
5 4 3 2
NAND Flash Controller
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