Source-Synchronous Timing Budget; Differential Data Orientation - Altera Cyclone V Device Handbook

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Figure 5-43: On-Chip Differential I/O Termination

Table 5-41: Quartus II Software Assignment Editor—On-Chip Differential Termination

This table lists the assignment name for on-chip differential termination in the Quartus II software Assignment

Assignment name

Source-Synchronous Timing Budget

The topics in this section describe the timing budget, waveforms, and specifications for source-synchronous

signaling in the Cyclone V device family.

The LVDS I/O standard enables high-speed transmission of data, resulting in better overall system

performance. To take advantage of fast system performance, you must analyze the timing for these high-

speed signals. Timing analysis for the differential block is different from traditional synchronous timing

analysis techniques.

The basis of the source synchronous timing analysis is the skew between the data and the clock signals instead

of the clock-to-output setup times. High-speed differential data transmission requires the use of timing

parameters provided by IC vendors and is strongly influenced by board skew, cable skew, and clock jitter.

This section defines the source-synchronous differential data orientation timing parameters, the timing

budget definitions for the Cyclone V device family, and how to use these timing parameters to determine

the maximum performance of a design.

There is a set relationship between an external clock and the incoming data. For operations at 840 Mbps

and a serialization factor of 10, the external clock is multiplied by 10. You can set phase-alignment in the

PLL to coincide with the sampling window of each data bit. The data is sampled on the falling edge of the

multiplied clock.

I/O Features in Cyclone V Devices

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Source-Synchronous Timing Budget

Differential Receiver

with On-Chip 100 Ω

Input Termination

Differential

Altera Corporation

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