Altera Cyclone V Device Handbook page 450

Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual
IEEE 1588-2002 Timestamps.....................................................................................................17-11
IEEE 1588-2008 Advanced Timestamps..................................................................................17-17
IEEE 802.3az Energy Efficient Ethernet...................................................................................17-19
Checksum Offload.......................................................................................................................17-19
Frame Filtering.............................................................................................................................17-20
Clocks and Resets.........................................................................................................................17-22
Resets.............................................................................................................................................17-22
Interrupts......................................................................................................................................17-23
Ethernet MAC Programming Model....................................................................................................17-23
DMA Controller...........................................................................................................................17-23
Descriptor Overview...................................................................................................................17-36
Descriptor Endianness................................................................................................................17-36
Descriptors....................................................................................................................................17-36
Initializing DMA..........................................................................................................................17-52
Initializing MAC..........................................................................................................................17-53
Performing Normal Receive and Transmit Operation...........................................................17-54
Stopping and Starting Transmission.........................................................................................17-54
Programming Guidelines for Energy Efficient Ethernet........................................................17-55
Programming Guidelines for Flexible Pulse-Per-Second (PPS) Output.............................17-56
Ethernet MAC Address Map and Register Definitions......................................................................17-58
Document Revision History...................................................................................................................17-58
USB 2.0 OTG Controller...................................................................................18-1
Features of the USB OTG Controller......................................................................................................18-2
Supported PHYs.............................................................................................................................18-3
USB OTG Controller Block Diagram and System Integration...........................................................18-4
Functional Description of the USB OTG Controller............................................................................18-5
USB OTG Controller Block Description....................................................................................18-5
ULPI PHY Interface......................................................................................................................18-8
Clocks..............................................................................................................................................18-9
Resets...............................................................................................................................................18-9
Interrupts......................................................................................................................................18-10
USB OTG Controller Programming Model.........................................................................................18-12
Enabling SPRAM ECCs..............................................................................................................18-12
Host Operation.............................................................................................................................18-12
Device Operation.........................................................................................................................18-14
USB OTG Controller Address Map and Register Definitions..........................................................18-15
Document Revision History...................................................................................................................18-16
TOC-11
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