Altera Cyclone V Device Handbook page 981

21-8
Transmit Watermark Level
Data should be fetched from the DMA often enough for the transmit FIFO to perform serial transfers
continuously, that is, when the FIFO begins to empty, another DMA request should be triggered. Otherwise,
the FIFO will run out of data (underflow) causing a STOP to be inserted on the UART bus. To prevent this
condition, you must set the watermark level correctly. †
Related Information
DMA Controller
For more information, refer to this DMA Controller chapter.
Transmit Watermark Level
Consider the example where the following assumption is made: †
DMA burst length = FIFO_DEPTH - decoded watermark level of IIR_FCR.TET †
Here the number of data items to be transferred in a DMA burst is equal to the empty space in the transmit
FIFO. Consider the following two different watermark level settings: †
IIR_FCR.TET = 1
IIR_FCR.TET = 1 decodes to a watermark level of 16.
• Transmit FIFO watermark level = decoded watermark level of IIR_FCR.TET = 16 †
• DMA burst length = FIFO_DEPTH - decoded watermark level of IIR_FCR.TET = 112 †
• UART transmit FIFO_DEPTH = 128 †
• Block transaction size =R** 448†
Figure 21-6: Transmit FIFO Watermark Level = 16
Transmit FIFO
Watermark Level
Data Out
The number of burst transactions needed equals the block size divided by the number of data items per
burst:
Block transaction size/DMA burst length = 448/112 = 4
The number of burst transactions in the DMA block transfer is 4. But the watermark level, decoded level of
IIR_FCR.TET, is quite low. Therefore, the probability of transmit underflow is high where the UART
serial transmit line needs to transmit data, but there is no data left in the transmit FIFO. This occurs because
the DMA has not had time to service the DMA request before the FIFO becomes empty.
IIR_FCR.TET = 3
IIR_FCR.TET = 3 decodes to a watermark level of 64.
Altera Corporation
on page 16-1
Transmit
FIFO Buffer
FIFO_DEPTH = 128
Empty
FIFO_DEPTH - IIR_FCR.TET = 112
Decoded watermark
Full
level of IIR_FCR.TET = 16
DMA
Controller
Data In
UART Controller
Send Feedback
cv_54021
2013.12.30