Altera Cyclone V Device Handbook page 153

5-56
True LVDS Buffers in Cyclone V Devices
Each I/O sub-bank can support up to two independent ALTLVDS interfaces. For example, you can place
two ALTLVDS interfaces in bank 8A driven by two different PLLs, provided that the LVDS channels are
not interleaved.
Table 5-35: LVDS Channels Supported in Cyclone V E Devices
Member Code
256-pin FineLine BGA
324-pin Ultra FineLine BGA
A2 and A4 383-pin Micro FineLine BGA
484-pin Ultra FineLine BGA
484-pin FineLine BGA
383-pin Micro FineLine BGA
A5 484-pin Ultra FineLine BGA
484-pin FineLine BGA
Altera Corporation
Package Side TX
Top 8
Left 4
Right 8
Bottom 12
Top 12
Left 8
Right 8
Bottom 16
Top 15
Left 12
Right 7
Bottom 16
Top 20
Left 4
Right 8
Bottom 24
Top 20
Left 4
Right 8
Bottom 24
Top 15
Right 7
Bottom 16
Top 20
Right 12
Bottom 24
Top 28
Right 8
Bottom 24
RX
8
4
8
12
12
8
8
16
19
12
8
20
20
4
8
24
20
4
8
24
19
8
21
20
12
24
28
8
24
I/O Features in Cyclone V Devices
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CV-52005
2014.01.10