Mlab - Altera Cyclone V Device Handbook

1-2

MLAB

Figure 1-1: LAB Structure and Interconnects Overview in Cyclone V Devices
This figure shows an overview of the Cyclone V LAB and MLAB structure with the LAB interconnects.
Connects to adjacent
LABs, memory blocks,
digital signal processing
(DSP) blocks, or I/O
element (IOE) outputs.
MLAB
Each MLAB supports a maximum of 640 bits of simple dual-port SRAM.
You can configure each ALM in an MLAB as a 32 x 2 memory block, resulting in a configuration of 32 x 20
simple dual-port SRAM block.
Altera Corporation
R14
R3/R6
Direct-Link
Interconnect from
Adjacent Block
Direct-Link
Interconnect to
Adjacent Block
Local Interconnect
C2/C4 C12
Row Interconnects of
Variable Speed and Length
LAB
Fast Local Interconnect Is Driven
from Either Sides by Column Interconnect
and LABs, and from Above by Row Interconnect
Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices
ALMs
Direct-Link
Interconnect from
Adjacent Block
Direct-Link
Interconnect to
Adjacent Block
MLAB
Column Interconnects of
Variable Speed and Length
Send Feedback
CV-52001
2014.01.10