Altera Cyclone V Device Handbook page 668

10-30
ECC Enabling
• If the device supports cache command sequences, enable the cache_write_enable and
cache_read_enable registers in the config group.
• Clear the flag bit of the copyback_disable register in the config group to 0 if the device does
not support the copyback command sequences. The register defaults to enabled state.
• The read_mode, write_mode and copyback_mode registers, in the config group, currently
need not be written by software, because the NAND flash controller is capable of using the correct
sequences based on a combination of some multi-plane or cache-related settings of the NAND flash
controller and the manufacturer ID. If at some future time these settings change, program the registers
to accommodate the change.
ECC Enabling
Before you start any data operation on the flash device, you need to decide whether you want to have the
ECC enabled or disabled. If the ECC needs to be enabled, then set up the appropriate correction level
depending on the page size and the spare area available on the device.
Set the flag bit in the ecc_enable register in the config group to 1 to enable ECC. If enabled, the
following registers in the config group need to be programmed accordingly, else they can be ignored.
• Initialize the ecc_correction register to the appropriate correction level.
• Program the spare_area_skip_bytes and spare_area_marker registers in the config
group if the software needs to preserve the bad block marker.
For detailed information about ECCs, refer to ECC.
Related Information
ECC on page 10-24
NAND Flash Controller Performance Registers
These registers specify the size of the bursts on the device interface, which maximizes the overall performance
on the NAND flash controller.
Initialize the flash_burst_length register in the dma group to a value which maximizes the performance
of the device interface by minimizing the number of bursts required to transfer a page.
Interrupt and DMA Enabling
Prior to initiating any data operation on the NAND flash controller, the software must set appropriate
interrupt status register bits. If the software chooses to use the DMA logic in the flash controller, then the
appropriate DMA enable and interrupts bits in the register space must be set.
1. Set the flag bit in the global_int_enable register in the config group to 1, to enable global
interrupt.
2. Set the relevant bits of the intr_en0 register in the status group to 1 before sending any operations
if the flash controller is in interrupt mode.
3. Enable DMA if your application needs DMA mode. Enable DMA by setting the flag bit of the
dma_enable register in the dma group. Altera recommends that the software reads back this register
to ensure that the mode change is accepted before sending a DMA command to the flash controller.
4. If the DMA is enabled, then set up the appropriate bits of the dma_intr_en register in the dma group.
Order of Interrupt Status Bits Assertion
The following interrupt status bits, in the intr_status0 register in the status group, are listed in the
order of interrupt bit setting:
Altera Corporation
cv_54010
2013.12.30
NAND Flash Controller
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