Altera Cyclone V Device Handbook page 575

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• Single event upset (SEU) protection
• Parity on Tag RAM
• ECC on L2 Data RAM
For more information about SEU errors, refer to the System Manager chapter in the Cyclone V Device
Handbook, Volume 3.
• Two slave ports mastered by the SCU
• Two master ports connected to the following slave ports:
• SDRAM controller, 64 bit slave port width
• L3 interconnect, 64 bit slave port width
• Cache lockdown capabilities as follows:
• Line lockdown
• Lockdown by way
• Lockdown by master (both processors and ACP masters)
• TrustZone support
• Cache event monitoring.
Table 6-7: AXI Cache Mode Support
Write-through
(16)
Write-back
Read allocate
Write allocate
Read and write allocate
Related Information
• L2 Cache Event Monitoring
• System Manager
L2 Cache Address Filtering
The L2 cache can access either the L3 interconnect fabric or the SDRAM. The L2 cache address filtering
determines how much address space is allocated to the HPS-to-FPGA bridge and how much is allocated to
SDRAM, depending on the configuration of the memory management unit.
Memory Management Unit describes how the address space is set based on L2 cache address filtering.
Related Information
• Cortex-A9 MPU Subsystem with L3 Interconnect
(16)
Restrictions exist when using ECCs. For more information about SEU protection, refer to the System Manager
chapter in the Cyclone V Device Handbook, Volume 3.
Cortex-A9 Microprocessor Unit Subsystem
Send Feedback
(16)
on page 6-31
on page 14-1
Cache Mode
on page 6-2
L2 Cache Address Filtering
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