Pipe Transceiver Datapath - Altera Cyclone V Device Handbook

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CV-53004
2013.10.17

PIPE Transceiver Datapath

Figure 4-2: Transceivers in a PCIe Hard IP Configuration
Note:
Refer to the Cyclone V Device Datasheet for the mgmt_clk_clk frequency specification when PCIe
HIP is used.
Transceiver Protocol Configurations in Cyclone V Devices
Send Feedback
Functional Mode
Data Rate (Gbps)
Number of Bonded Channels
PMA–PCS Interface Width
Word Aligner (Pattern)
8B/10B Encoder/Decoder
Rate Match FIFO
PCIe Hard IP
Byte SERDES
PCS–Hard IP Interface Width
(Per lane)
PCS–Hard IP Interface Frequency
PIPE Transceiver Datapath
PCIe HIP
2.5 for Gen1
5 for Gen2
x1, x2, x4
10-Bit
Automatic Synchronization
State Machine (/K28.5+/K28.5-/)
Enabled
Enabled
Enabled
Disabled
8-Bit
Gen1 - 250 MHz
Gen2 - 500 MHz
4-3
Altera Corporation

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