Altera Cyclone V Device Handbook page 942

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2013.12.30
• Write Control Register 0 (CTRLLR0). For SPI transfers, you must set the serial clock polarity and
serial clock phase parameters identical to the target slave device.
• If the transfer mode is receive only, write Control Register 1 (CTRLR1) with the number of frames
in the transfer minus 1. For example, if you want to receive four data frames, write this register with
3.
• Write the Baud Rate Select Register (BAUDR) to set the baud rate for the transfer.
• Write the Transmit and Receive FIFO Threshold Level registers (TXFTLR and RXFTLR) to set FIFO
buffer threshold levels.
• Write the IMR register to set up interrupt masks.
• Write the Slave Enable Register (SER) register here to enable the target slave for selection. If a slave
is enabled here, the transfer begins as soon as one valid data entry is present in the transmit FIFO
buffer. If no slaves are enabled prior to writing to the Data Register (DR), the transfer does not begin
until a slave is enabled.
3. Enable the SPI master by writing 1 to the SSIENR register.
4. Write data for transmission to the target slave into the transmit FIFO buffer (write DR). If no slaves were
enabled in the SER register at this point, enable it now to begin the transfer.
5. Poll the BUSY status to wait for the transfer to complete. If a transmit FIFO empty interrupt request is
made, write the transmit FIFO buffer (write DR). If a receive FIFO full interrupt request is made, read
the receive FIFO buffer (read DR).
SPI Controller
Send Feedback
Master SPI and SSP Serial Transfers
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