Uart Controller Address Map And Register Definitions - Altera Cyclone V Device Handbook

21-10
Receive FIFO Overflow
Receive FIFO Overflow
During UART serial transfers, receive FIFO requests are made to the DMA whenever the number of entries
in the receive FIFO is at or above the decoded level of Receive Trigger (RT) field in the FIFO Control Register
(IIR_FCR). This is known as the watermark level. The DMA responds by fetching a burst of data from the
receive FIFO. †
Data should be fetched by the DMA often enough for the receive FIFO to accept serial transfers continuously,
that is, when the FIFO begins to fill, another DMA transfer is requested. Otherwise the FIFO will fill with
data (overflow). To prevent this condition, the user must set the watermark level correctly. †
Receive Watermark Level
Similar to choosing the transmit watermark level described earlier, the receive watermark level, decoded
watermark level of IIR_FCR.RT, should be set to minimize the probability of overflow, as shown in the
Receive FIFO Buffer diagram. It is a tradeoff between the number of DMA burst transactions required per
block versus the probability of an overflow occurring. †
Receive FIFO Underflow
Setting the source transaction burst length greater than the watermark level can cause underflow where there
is not enough data to service the source burst request. Therefore, the following equation must be adhered
to avoid underflow: †
DMA burst length = decoded watermark level of IIR_FCR.RT + 1
If the number of data items in the receive FIFO is equal to the source burst length at the time of the burst
request is made, the receive FIFO may be emptied, but not underflowed, at the completion of the burst
transaction. For optimal operation, DMA burst length should be set at the watermark level, decoded watermark
level of IIR_FCR.RT. †
Adhering to this equation reduces the number of DMA bursts in a block transfer, which in turn can avoid
underflow and improve bus utilization. †
The receive FIFO will not be empty at the end of the source burst transaction if the UART controller has
successfully received one data item or more on the UART serial receive line during the burst. †
Figure 21-8: Receive FIFO Buffer
Receive FIFO
Watermark Level

UART Controller Address Map and Register Definitions

The address map and register definitions reside in the hps.html file that accompanies this handbook volume.
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Altera Corporation
FIFO Buffer
Data In
Receive
Empty
Data Out
Decoded watermark
Full
level of IIR_FCR.RT
cv_54021
2013.12.30
DMA
Controller
UART Controller
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