Altera Cyclone V Device Handbook page 84

CV-52004
2014.01.10
Figure 4-26: Example of Phase Relationship Between the Clock and Data in LVDS Compensation Mode
Direct Mode
In direct mode, the PLL does not compensate for any clock networks. This mode provides better jitter
performance because the clock feedback into the PFD passes through less circuitry. Both the PLL internal-
and external-clock outputs are phase-shifted with respect to the PLL clock input.
Figure 4-27: Example of Phase Relationship Between the PLL Clocks in Direct Mode
Normal Compensation Mode
An internal clock in normal compensation mode is phase-aligned to the input clock pin. The external clock
output pin has a phase delay relative to the clock input pin if connected in this mode. The Quartus II
TimeQuest Timing Analyzer reports any phase difference between the two. In normal compensation mode,
the delay introduced by the GCLK or RCLK network is fully compensated.
Clock Networks and PLLs in Cyclone V Devices
Send Feedback
Data Pin
PLL Reference Clock
at the Input Pin
Data at the Register
Clock at the Register
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port
The PLL clock outputs
lag the PLL input clocks
depending on routing
delays.
External PLL
Clock Outputs
Phase Aligned
4-27
Direct Mode
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