Altera Cyclone V Device Handbook page 396

4-14
Gigabit Ethernet Transceiver Datapath
Figure 4-15: Transceiver Datapath in GbE-3.125 Gbps Configuration
FPGA Fabric
tx_coreclk[0]
FPGA Fabric–Transceiver Interface Clock
rx_coreclk[0]
Table 4-4: Transceiver Datapath Clock Frequencies in GbE Configuration
Functional Mode Data Rate
GbE-1.25 1.25 Gbps
Gbps
GbE-3.125 3.125 Gbps
Gbps
8B/10B Encoder
In GbE configuration, the 8B/10B encoder clocks in 8-bit data and 1-bit control identifiers from the transmitter
phase compensation FIFO and generates 10-bit encoded data. The 10-bit encoded data is fed to the serializer.
For more information about the 8B/10B encoder functionality, refer to the
Cyclone V Devices
Rate Match FIFO
In GbE configuration, the rate match FIFO is capable of compensating for up to ±100 ppm (200 ppm total)
difference between the upstream transmitter and the local receiver reference clock. The GbE protocol requires
that the transmitter send idle ordered sets /I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during interpacket
gaps, adhering to the rules listed in the IEEE 802.3 specification.
The rate match operation begins after the synchronization state machine in the word aligner indicates that
the synchronization is acquired-by driving the rx_syncstatus signal high. The rate matcher always
deletes or inserts both symbols (/K28.5/ and /D16.2/) of the /I2/ ordered sets, even if only one symbol needs
to be deleted to prevent the rate match FIFO from overflowing or underrunning. The rate matcher can insert
or delete as many /I2/ ordered sets as necessary to perform the rate match operation.
Altera Corporation
TX Phase
Byte 8B/10B
Compensation
SERDES Encoder
FIFO
wrclk rdclk
Low-Speed Parallel Clock
tx_clkout[0]
RX Phase
Byte
Compensation
Decoder
SERDES
FIFO
Low-Speed Parallel Clock
High-Speed Serial
Clock Frequency
625 MHz
1562.5 MHz
chapter.
Transmitter Channel PCS
Receiver Channel PCS
Rate
8B/10B
Word
Match
Aligner
FIFO
Parallel Recovered Clock
Parallel Recovered
Clock and Low-Speed
Parallel Clock
Frequency
125 MHz
312.5 MHz
Transceiver Protocol Configurations in Cyclone V Devices
Transmitter Channel PMA
Serializer
High-Speed Serial Clock
Local Clock
Divider
Receiver Channel PMA
Deserializer CDR
FPGA Fabric-Transceiver Interface
Clock Frequency
125 MHz
156.25 MHz
Transceiver Architecture for
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CV-53004
2013.10.17