Multiplier Adder Sum Mode; 18 X 18 Multiplication Summed With 36-Bit Input Mode; Systolic Fir Mode - Altera Cyclone V Device Handbook

CV-52003
2014.01.10

Multiplier Adder Sum Mode

Figure 3-11: One Sum of Two 18 x 19 Multipliers with One Variable Precision DSP Block for Cyclone V
Devices
SUB_COMPLEX
dataa_y0[18..0]
dataa_x0[17..0]
datab_y1[18..0]
datab_x1[17..0]

18 x 18 Multiplication Summed with 36-Bit Input Mode

Cyclone V variable precision DSP blocks support one 18 x 18 multiplication summed to a 36-bit input.
Use the upper multiplier to provide the input for an 18 x 18 multiplication, while the bottom multiplier is
bypassed. The
Figure 3-12: One 18 x 18 Multiplication Summed with 36-Bit Input Mode for Cyclone V Devices
SUB_COMPLEX
dataa_y0[17..0]
dataa_x0[17..0]
datab_y1[35..18]
datab_y1[17..0]

Systolic FIR Mode

The basic structure of a FIR filter consists of a series of multiplications followed by an addition.
Variable Precision DSP Blocks in Cyclone V Devices
Send Feedback
Variable-Precision DSP Block
19
18
19
18
and
datab_y1[17..0] datab_y1[35..18]
Variable-Precision DSP Block
Multiplier
18
x
18
18
18
Multiplier
x
+/-
Multiplier
Adder
x
signals are concatenated to produce a 36-bit input.
Chainout adder or
accumulator
+
+/-
Adder
Multiplier Adder Sum Mode
Chainout adder or
accumulator
38
+
37
3-15
Result[37..0]
Result[36..0]
Altera Corporation