Altera Cyclone V Device Handbook page 442

Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual
HPS External Reset Sources............................................................................................................3-3
Reset Controller................................................................................................................................3-4
Module Reset Signals.......................................................................................................................3-5
Slave Interface and Status Register................................................................................................3-9
Functional Description of the Reset Manager.........................................................................................3-9
Reset Sequencing............................................................................................................................3-10
Reset Pins........................................................................................................................................3-12
Reset Effects....................................................................................................................................3-13
Altering Warm Reset System Response......................................................................................3-13
Reset Handshaking........................................................................................................................3-14
Reset Manager Address Map and Register Definitions........................................................................3-14
Document Revision History.....................................................................................................................3-15
Interconnect.........................................................................................................4-1
Features of the Interconnect.......................................................................................................................4-1
Interconnect Block Diagram and System Integration............................................................................4-2
L3 Masters.........................................................................................................................................4-4
L3 Slaves............................................................................................................................................4-4
L4 Slaves............................................................................................................................................4-6
Functional Description of the Interconnect.............................................................................................4-7
Master to Slave Connectivity Matrix.............................................................................................4-7
Address Remapping.........................................................................................................................4-9
Master Caching and Buffering Overrides...................................................................................4-12
Security............................................................................................................................................4-13
Arbitration......................................................................................................................................4-13
Cyclic Dependency Avoidance Schemes....................................................................................4-13
Interconnect Master Properties...................................................................................................4-14
Interconnect Slave Properties.......................................................................................................4-15
Upsizing Data Width Function....................................................................................................4-17
Downsizing Data Width Function..............................................................................................4-18
Lock Support..................................................................................................................................4-19
FIFO Buffers and Clocks...............................................................................................................4-19
Resets...............................................................................................................................................4-19
Interconnect Address Map and Register Definitions...........................................................................4-20
Document Revision History.....................................................................................................................4-20
HPS-FPGA AXI Bridges......................................................................................5-1
Features of the AXI Bridges........................................................................................................................5-1
TOC-3
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