Dynamic Reconfiguration Of Loopback Modes; Transceiver Pll Reconfiguration - Altera Cyclone V Device Handbook

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Dynamic Reconfiguration of Loopback Modes

Related Information
Altera Transceiver PHY IP Core User Guide
For information about the read and write operations with the reconfiguration controller
Dynamic Reconfiguration of Loopback Modes
You can enable the pre- and post-CDR reverse serial loopback modes by writing the appropriate bits of the
Transceiver Reconfiguration Controller
The following loopback paths are available:
• Post-CDR reverse serial loopback path— The RX captures the input data and feeds it into the CDR.
The recovered data from the CDR output feeds into the TX driver and sends to the TX pins through the
TX driver. For this path, the RX and CDR can be tested. For this path, the TX driver can be programmed
to use either the main tap only or the main tap and the pre-emphasis first post-tap. Enabling or disabling
the post-CDR reverse serial loopback modes is done through the PMA Analog Reconfiguration IP in the
Transceiver Reconfiguration PHY IP.
• Pre-CDR reverse serial loopback path— The RX captures the input data and feeds it back to the TX
driver through a buffer. With this path, you can perform a quick check for the quality of the RX and TX
buffers. Enabling or disabling the pre-CDR reverse serial loopback mode.
Note: Serial loopback can be implemented with the transceiver PHY IP directly using the Avalon interface
or a control port.
Related Information
• Transceiver Reconfiguration Controller chapter of the Altera Transceiver PHY IP Core User Guide
• Transceiver Loopback Support in Cyclone V Devices

Transceiver PLL Reconfiguration

You can use the PLL reconfiguration registers to switch the reference clock input to the TX PLL or the clock
data recovery (CDR) circuitry.
For example, you can switch the reference clock from 100 MHz to 125 MHz. You can also change the data
rate from 2.5 Gbps to 5 Gbps by reconfiguring the transmitter PLL connected to the transceiver channel.
Note: Reference clock switching is only supported on the dedicated REFCLK pin.
The Transceiver Reconfiguration PHY IP provides an Avalon
reconfiguration.
Related Information
"PLL Reconfiguration" section in the Transceiver Reconfiguration Controller chapter of the Altera
Transceiver PHY IP Core User Guide
For information about performing PLL reconfiguration.
Altera Corporation
®
-MM user interface to perform PLL
Dynamic Reconfiguration in Cyclone V Devices
CV-53007
2013.05.06
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