Altera Cyclone V Device Handbook page 493

cv_54002
2013.12.30
Module Name
SD/MMC controller
EMAC 0
EMAC 1
USB 0
USB 1
NAND flash controller
OSC1 timer 0
OSC1 timer 1
SP timer 0
SP timer 1
I2C controller 0
I2C controller 1
Clock Manager
Send Feedback
System Clock Name
qspi_clk
l4_mp_clk
sdmmc_clk
l4_mp_clk
emac0_clk
osc1_clk
l4_mp_clk
emac1_clk
osc1_clk
usb_mp_clk
usb_mp_clk
nand_x_clk
nand_clk
osc1_clk
osc1_clk
l4_sp_clk
l4_sp_clk
l4_sp_clk
Clock Usage By Module
Use
Reference clock for serialization
Clock for the master and slave
Clock for the SD/MMC internal
logic
Clock for the master
EMAC 0 internal logic clock
IEEE 1588 timestamp clock
Clock for the master
EMAC 1 internal logic clock
IEEE 1588 timestamp clock
Clock for the master and slave
Clock for the master and slave
NAND high-speed master and
slave clock
NAND flash clock
Clock for the OSC1 timer 0
Clock for the OSC1 timer 1
Clock for the SP timer 0
Clock for the SP timer 1
Clock for the I2C 0
Clock for the I2C 1
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