Altera Cyclone V Device Handbook page 205

CV-52006
2014.01.10
Feature
Memory Density
Memory Burst Length
Command and Data
Reordering
Starvation Control
User-Configurable
Priority Support
®
Avalon -MM Data
Slave Local Interface
Bank Management
Streaming Reads and
Writes
Bank Interleaving
Predictive Bank
Management
Multiport Interface
Built-in Burst
Adaptor
Run-time Configura-
tion of the Controller
On-Die Termination
User-Controlled
Refresh Timing
External Memory Interfaces in Cyclone V Devices
Send Feedback
The controller supports up to four gigabits density parts and two chip selects.
DDR3—Burst length of 8 and burst chop of 4
DDR2—Burst lengths of 4 and 8
LPDDR2—Burst lengths of 2, 4, 8, and 16
The controller increases efficiency through the support for out-of-order execution
of DRAM commands—with address collision detection-and in-order return of results.
A starvation counter ensures that all requests are served after a predefined time-out
period. This function ensures that data with low priority access are not left behind
when reordering data for efficiency.
When the controller detects a high priority request, it allows the request to bypass
the current queuing request. This request is processed immediately and thus reduces
latency.
By default, the controller supports the Avalon Memory-Mapped protocol.
By default, the controller provides closed-page bank management on every access.
The controller intelligently keeps a row open based on incoming traffic. This feature
improves the efficiency of the controller especially for random traffic.
The controller can issue reads or writes continuously to sequential addresses every
clock cycle if the bank is open. This function allows for very high efficiencies with
large amounts of data.
The controller can issue reads or writes continuously to 'random' addresses.
The controller can issue bank management commands early so that the correct row
is open when the read or write occurs. This increases efficiency.
The interface allows you to connect up to six data masters to access the memory
controller through the local interface. You can update the multiport scheduling
configuration without interrupting traffic on a port.
The controller can accept bursts of arbitrary sizes on its local interface and map these
bursts to efficient memory commands.
This feature provides support for updates to the timing parameters without requiring
reconfiguration of the FPGA, apart from the standard compile-time setting of the
timing parameters.
The controller controls the on-die termination (ODT) in the memory, which improves
signal integrity and simplifies your board design.
You can optionally control when refreshes occur—allowing the refreshes to avoid
clashing of important reads or writes with the refresh lock-out time.
Features of the Hard Memory Controller
Description
6-31
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