Altera Cyclone V Device Handbook page 125

5-28
I/O Buffer and Registers in Cyclone V Devices
Table 5-23: Input and Output Paths in Cyclone V Devices
This table summarizes the input and output path in the Cyclone V devices.
Consists of:
DDR input registers
Alignment and synchronization registers
Half data rate blocks
You can bypass each block in the input path. The
input path uses the deskew delay to adjust the input
register clock delay across process, voltage, and
temperature (PVT) variations.
Figure 5-10: IOE Structure for Cyclone V Devices
This figure shows the Cyclone V FPGA IOE structure. In the figure, one dynamic on-chip termination (OCT)
control is available for each DQ/DQS group.
From Core
OE
from
Core
Write
Data
from
Core
clkout
To
Core
To
Core
Read
Data
to
Core
DQS
CQn
clkin
Altera Corporation
Input Path
2
Half Data
Rate Block
OE Register
Output Register
4 Half Data
Rate Block
Output Register
D3_1
Delay
Same avalaible settings in
the Quartus II software
4
Read
FIFO
D4 Delay
Consists of:
Output or
OE
Alignment registers
Half data rate blocks
You can bypass each block of the output and
OE Register
PRN
D Q
PRN
D Q
Programmable
Current
Strength and
PRN
D Q Slew Rate
Control
D5 Delay
Open Drain
PRN
D Q
D3_0
Delay
D1
Delay
Input Register
PRN
D Q
Input Register Input Register
PRN PRN
D Q D Q
Output Path
registers
DQS Logic Block
D5_OCT
Dynamic OCT Control
D5 Delay
V CCIO
V CCIO
Programmable
Pull-Up Resistor
Optional
PCI Clamp
From OCT
Calibration
Block
Output
Buffer
On-Chip
Termination
Input Buffer
Bus-Hold
Circuit
I/O Features in Cyclone V Devices
CV-52005
2014.01.10
paths.
OE
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