Singleport Controller - Altera Cyclone V Device Handbook

8-6

SinglePort Controller

Read Data Block
The read data block receives data from the single-port controller. Depending on the port state, the read data
block either buffers the data in its internal buffer or passes the data straight to the clock boundary crossing
FIFO buffer. The read data block reorders out-of-order data for Avalon-MM ports.
In order to prevent the read FIFO buffer from overflowing, the read data block informs the command block
of the available buffer area so the command block can pace read transaction dispatch.
SinglePort Controller
The single-port logic is responsible for following actions:
• Queuing the pending SDRAM bursts
• Choosing the most efficient burst to send next
• Keeping the SDRAM pipeline full
• Ensuring all SDRAM timing parameters are met
Transactions passed to the single-port logic for a single page in SDRAM are guaranteed to be executed in
order, but transactions can be reordered between pages. Each SDRAM burst read or write is converted to
the appropriate Altera PHY interface (AFI) command to open a bank on the correct row for the transaction
(if required), execute the read or write command, and precharge the bank (if required).
The single-port logic implements command reordering (looking ahead at the command sequence to see
which banks can be put into the correct state to allow a read or write command to be executed) and data
reordering (allowing data transactions to be dispatched even if the data transactions are executed in an order
different than they were received from the multiport logic).
Command Generator
The command generator accepts commands from the MPFE and from the internal ECC logic, and provides
those commands to the timer bank pool.
Timer Bank Pool
The timer bank pool is a parallel queue that operates with the arbiter to enable data reordering. The timer
bank pool tracks incoming requests, ensures that all timing requirements are met, and, on receiving write-
data-ready notifications from the write data buffer, passes the requests to the arbiter.
Arbiter
The arbiter determines the order in which requests are passed to the memory device. When the arbiter
receives a single request, that request is passed immediately. When multiple requests are received, the arbiter
uses arbitration rules to determine the order to pass requests to the memory device.
Rank Timer
The rank timer performs the following functions:
• Maintains rank-specific timing information
• Ensures that only four activates occur within a specified timing window
• Manages the read-to-write and write-to-read bus turnaround time
• Manages the time-to-activate delay between different banks
Altera Corporation
cv_54008
2013.12.30
SDRAM Controller Subsystem
Send Feedback