Dq/Dqs Groups In Cyclone V St; External Memory Interface Features In Cyclone V Devices; Uniphy Ip - Altera Cyclone V Device Handbook

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DQ/DQS Groups in Cyclone V ST

DQ/DQS Groups in Cyclone V ST
Table 6-10: Number of DQ/DQS Groups Per Side in Cyclone V ST Devices
This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the
DQ/DQS groups from the pin table of the specific device. The numbers are preliminary before the devices are
available.
Member Code
D5
896-pin FineLine BGA
D6
Related Information
Cyclone V Device Pin-Out Files
Download the relevant pin tables from this web page.

External Memory Interface Features in Cyclone V Devices

The Cyclone V I/O elements (IOE) provide built-in functionality required for a rapid and robust
implementation of external memory interfacing.
The following device features are available for external memory interfaces:
DQS phase-shift circuitry
PHY Clock (PHYCLK) networks
DQS logic block
Dynamic on-chip termination (OCT) control
IOE registers
Delay chains
Hard memory controllers

UniPHY IP

The high-performance memory interface solution includes the self-calibrating UniPHY IP that is optimized
to take advantage of the Cyclone V I/O structure and the Quartus II software TimeQuest Timing Analyzer.
The UniPHY IP helps set up the physical interface (PHY) best suited for your system. This provides the total
solution for the highest reliable frequency of operation across process, voltage, and temperature (PVT)
variations.
The UniPHY IP instantiates a PLL to generate related clocks for the memory interface. The UniPHY IP can
also dynamically choose the number of delay chains that are required for the system. The amount of delay
is equal to the sum of the intrinsic delay of the delay element and the product of the number of delay steps
and the value of the delay steps.
The UniPHY IP and the Altera memory controller MegaCore
frequency of the memory devices, allowing better timing management in high-speed memory interfaces.
The Cyclone V devices contain built-in circuitry in the IOE to convert data from full rate (the I/O frequency)
to half rate (the controller frequency) and vice versa.
Altera Corporation
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functions can run at half the I/O interface
External Memory Interfaces in Cyclone V Devices
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