Altera Cyclone V Device Handbook page 303

1-16
Receiver Buffer
Block
Channel PLL
Deserializer
Receiver Buffer
Table 1-7: Cyclone Receiver Buffer Features
Category
Improve Signal
Integrity
Save Board Space and
Cost
Reduce Power
Altera Corporation
• Recovers the clock and serial data stream if you configure the channel
PLL as a CDR.
• Requires offset cancellation to correct the analog offset voltages.
• If you do not use the channel PLL as a CDR, you can configure the
channel PLL as a CMU PLL for clocking the transceivers.
• Converts the incoming high-speed serial data from the receiver buffer
to low-speed parallel data for the receiver PCS.
• Receives serial data in LSB-to-MSB order.
• Supports 8-, 10-, 16-, and 20-bit deserialization factors.
• Supports the optional clock-slip feature for applications with stringent
latency uncertainty requirement.
Features
Programmable Boosts the high-frequency components of the received signal,
Continuous Time which may be attenuated when propagating through the
Linear transmission medium. The physical transmission medium can be
Equalization represented as a low-pass filter in the frequency domain. Variation
(CTLE) in the signal frequency response that is caused by attenuation leads
to data-dependent jitter and other ISI effects—causing incorrect
sampling on the input data at the receiver. The amount of the
high-frequency boost required at the receiver to overcome signal
attenuation depends on the loss characteristics of the physical
medium.
Programmable Provides equal boost to the received signal across the frequency
DC Gain spectrum.
On-Chip Biasing Establishes the required receiver common-mode voltage (RX V
level at the receiver input. The circuitry is available only if you
enable OCT. When you disable OCT, you must implement off-
chip biasing circuitry to establish the required RX V
Differential OCT The termination resistance is adjusted by the calibration circuitry,
which compensates for PVT. You can disable OCT and use
external termination. However, you must implement off-chip
biasing circuitry to establish the required RX V
is tri-stated when you use external termination.
Programmable Controls the impedance of V
V Current reduces current consumption from the on-chip biasing circuitry.
CM
Strength
Functionality
Description
CM
. A higher impedance setting
CM
Transceiver Architecture in Cyclone V Devices
CV-53001
2013.05.06
)
CM
level.
CM
level. RX V
CM
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