Resetting The Receiver With The User-Coded Reset Controller During Device Power-Up Configuration - Altera Cyclone V Device Handbook

CV-53003

Resetting the Receiver with the User-Coded Reset Controller during Device Power-Up Configuration

2013.05.06
3. Deassert tx_digitalreset after a minimum duration of t
are removed:
• pll_powerdown is deasserted
• pll_locked is deasserted
Figure 3-6: Reset Sequence Timing Diagram for Transmitter using the User-Coded Reset Controller
during Device Operation
Resetting the Receiver with the User-Coded Reset Controller during Device Power-Up
Configuration
Follow this reset sequence to ensure a reliable receiver initialization after the initial power-up.
The numbers in the following figure correspond to the following numbered list, which guides you through
the receiver reset sequence during device power-up.
1. Assert mgmt_rst_reset at power-up to start the calibration IPs. Hold mgmt_rst_reset active
for a minimum of two mgmt_clk_clock cycles. Hold rx_analogreset and rx_digitalreset
active at power-up to hold the receiver in reset. You can deassert them after all the gating conditions are
removed.
2. After the receiver calibration completes, the rx_cal_busy status is de-asserted.
3. Deassert rx_analogreset after a minimum duration of t
4. rx_is_lockedtodata is a status signal from the receiver CDR indicating that the CDR is in the lock
to data (LTD) mode. Ensure rx_is_lockedtodata is asserted and stays asserted for a minimum
duration of t
toggles, you must wait another additional t
5. Deassert rx_digitalreset after a minimum duration of t
asserted. Ensure rx_analogreset and rx_cal_busy are deasserted before deasserting
rx_digitalreset.
The receiver is now out of reset and ready for operation.
Note: rx_is_lockedtodata might toggle when there is no data at the receiver
input.
Transceiver Reset Control in Cyclone V Devices
Send Feedback
mgmt_rst_reset 1
1
pll_powerdown
tx_analogreset 1
tx_digitalreset 1
pll_locked
tx_cal_busy
before deasserting rx_digitalreset. If rx_is_lockedtodata is asserted and
LTD
tx_digitalreset
t min 1 μs
pll_powerdown
3
t min 20ns
tx_digitalreset
2 t max 10 μs
pll_lock
rx_analogreset
duration before deasserting rx_digitalreset.
LTD
LTD
, and after all the gating conditions
after rx_cal_busy is deasserted.
after rx_is_lockedtodata stays
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3-9