Sd/Mmc/Ce-Ata Protocol; Biu - Altera Cyclone V Device Handbook

11-4

SD/MMC/CE-ATA Protocol

SD/MMC/CE-ATA Protocol
The SD/MMC/CE-ATA protocol is based on command and data bit streams that are initiated by a start bit
and terminated by a stop bit. Additionally, the SD/MMC controller provides a reference clock and is the
only master interface that can initiate a transaction.
• Command a token transmitted serially on the CMD pin that starts an operation.
• Response a token from the card transmitted serially on the CMD pin in response to certain commands.
• Data transferred serially using the data pins for data movement commands.
In the following figure, the clock is a representative only and does not show the exact number of clock cycles.
Figure 11-2: Multiple-Block Read Operation
sdmmc_cclk_out
sdmmc_cmd
sdmmc_data
The following figure illustrates an example of a command token sent by the host in a multiple-block write
operation.
Figure 11-3: Multiple-Block Write Operation
sdmmc_cclk_out
sdmmc_cmd
sdmmc_data

BIU

The BIU interfaces with the CIU, and is connected to the level 3 (L3) interconnect and level 4 (L4) peripheral
buses. The BIU consists of the following primary functional blocks, which are defined in the following
sections:
Altera Corporation
†
From Host From Card Data from
to Card to Host Card to Host
Command Response
Data Block CRC
Block Read Operation
Multiple Block Read Operation
†
From Host From Card Data from
to Card to Host Host to Card
Command Response
Data Block
Block Write Operation
Multiple Block Read Operation
†
Command
Data Block CRC Data Block
Data Stop Operation
OK Response &
Busy from Card
Command
CRC Busy Data Block
Data Stop Operation
†
†
Stop Command
Stops Data Transfer
Response
CRC
Stop Command
Stops Data Transfer
Response
CRC Busy
SD/MMC Controller
Send Feedback
cv_54011
2013.12.30
†
†