Deterministic Latency Protocols-Cpri And Obsai; Latency Uncertainty Removal With The Phase Compensation Fifo In Register Mode; Channel Pll Feedback For Deterministic Relationship - Altera Cyclone V Device Handbook

CV-53004
2013.10.17
Deterministic Latency Protocols—CPRI and OBSAI
A deterministic latency option is available for use in high-speed serial interfaces such as the Common Public
Radio Interface (CPRI) and OBSAI Reference Point 3 (OBSAI RP3). Both CPRI and OBSAI RP3 protocols
place stringent requirements on the amount of latency variation that is permissible through a link that
implements these protocols.
Figure 4-28: Transceiver Datapath in Deterministic Latency Mode
FPGA
Fabric

Latency Uncertainty Removal with the Phase Compensation FIFO in Register Mode

To remove the latency uncertainty through the receiver's phase compensation FIFO, the receiver and
transmitter phase compensation FIFOs are always set to register mode. In register mode, the phase
compensation FIFO acts as a register and thereby removes the uncertainty in latency. The latency through
the transmitter and receiver phase compensation FIFO in register mode is one clock cycle.
The following options are available:
• Single-width mode with 8-bit channel width and 8B/10B encoder enabled or 10-bit channel width with
8B/10B disabled
• Double-width mode with 16-bit channel width and 8B/10B encoder enabled or 20-bit channel width with
8B/10B disabled

Channel PLL Feedback for Deterministic Relationship

To implement the deterministic latency functional mode, the phase relationship between the low-speed
parallel clock and channel PLL input reference clock must be deterministic. A feedback path is enabled to
ensure a deterministic relationship between the low-speed parallel clock and channel PLL input reference
clock.
To achieve deterministic latency through the transceiver, the reference clock to the channel PLL must be
the same as the low-speed parallel clock. For example, if you need to implement a data rate of 1.2288 Gbps
for the CPRI protocol, which places stringent requirements on the amount of latency variation, you must
choose a reference clock of 122.88 MHz to allow the usage of a feedback path from the channel PLL. This
feedback path reduces the variations in latency.
Transceiver Protocol Configurations in Cyclone V Devices
Send Feedback
Deterministic Latency Protocols—CPRI and OBSAI
Transmitter Channel PCS
TX Phase
Compensation
Byte Serializer
FIFO
wrclk rdclk wrclk rdclk
Receiver Channel PCS
8B/10B Encoder
Transmitter Channel Datapath
Receiver Channel Datapath
4-29
Transmitter Channel
PMA
Receiver Channel
PMA
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