Altera Cyclone V Device Handbook page 405

CV-53004
2013.10.17
Figure 4-22: Transceiver Clocking for XAUI Soft PCS Implementation
Channel 3
Channel 2
Channel 1
Channel 0
xgmii_tx_clk
16
xgmii_rx_clk
Transceiver Channel Placement Guidelines
In the soft PCS implementation of the XAUI configuration, all four channels must be placed continuously.
The channels may all be placed in one bank or they may span two banks. Only the placements shown in the
following figure are allowed.
Transceiver Protocol Configurations in Cyclone V Devices
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Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration
FPGA Fabric
Soft PCS
Soft PCS
16 20
20
Parallel Clock
Parallel Clock
(Recovered) from Channel 0
CMU PLL
(From the ×1 Clock Lines)
Channel 3
Soft PCS
Soft PCS Channel 2
Channel 1
Channel 0
Central/ Local Clock Divider
Serial Clock
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Transmitter Standard PCS
Transmitter Standard PCS
Transmitter Standard PCS
Transmitter Standard PCS
20 10
Parallel Clock
/2
Receiver Standard PCS
20 10
/2
Parallel Clock (Recovered)
Clock Divider
4-23
Transmitter PMA Ch 3
Transmitter PMA Ch 2
Transmitter PMA Ch 1
Transmitter PMA Ch 0
Receiver PMA
Parallel Clock
Serial Clock
Parallel and Serial Clocks
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